Chapter 1: Overview of the Design Process
Before a design team begins a new board, an initial design review is completed. This review determines the overall functionality, performance, operating conditions, footprint and technology that are needed to complete the PCB design objectives. This design specification is then used as the basis for a cost analysis. During the evaluation phase, a number of factors must be considered. This study lays out a design schedule and assesses total development costs as well as an estimate of the unit manufacturing costs to fabricate and build each board. Equally important is determining whether or not the board will require special processing or tooling which might add to the overall cost structure. Once all of these factors have been assessed, the system specifications can then be used as a starting point to begin the design process.
System Block Diagram
The first step in the design process is to create a block diagram of all the major functions that are needed for each board and how each functional block will be linked to the other blocks. It's a high-level, visual layout that describes which functions each block will perform and how they'll interact with each other. As such, the diagram is a road map for each functional block's relationship to other functional blocks and how it will communicate with them. Usually, this global block diagram then takes each major block and breaks it down into smaller blocks until such time as the blocks are essentially schematic diagrams.
Using the block diagram as a reference point, the designer will divide the circuits into PCB packets that group functions that must work together and interact frequently on the same PCB. Usually, this partitioning is done to facilitate data busing communcationcommunication between the various functional blocks. This grouping of functions is important for ensuring that the board can meet the design objectives specified, such as the size and number of connections between partitions that are allowed. Also, a logical grouping of functions helps to balance each partition with its neighboring functional blocks and minimize the trace lengths and the number of interconnects required. This reduces propagation delays between the different partitions when they need to send or receive data to other functional blocks.
Sizing the PCB Footprint
Generally, the PCB dimensions are known in advance. Based on the intended application, a standard footprint has usually been established by Joint Electron Devices Engineering Council (JEDEC ) and the IPC-7351B Generic Requirements for Surface Mount Design & Land Pattern Standards. This is a trade consortium of influential companies that determines standard package sizes that must be adhered to in the design and fabrication of each board. This standard will dictate the number of components that can be fitted onto each standard-size board. If the PCB size is not fixed, then the board designer has the freedom to determine what size footprint should be used to fit all of the components and circuitry onto the same board. The designer must, however, make sure that the board can fit into the overall design concept. Knowing the overall footprint, the designer now has the challenge of devising the most efficient and economical way to utilize a panel's space real estate to come up with the most cost effective solution.
Creating the Circuit Schematic
After the block diagram and system partitioning have been completed, the designer can start building a circuit schematic. The schematic is simply a graphical representation of all of the components that will be used in each circuit. By convention, the various components are represented by different symbols or CAE decals by certain schematic capture tools.
• IEC 60617 (also known as British Standard BS 3939)
• ANSI standard Y32 (also known as IEEE Std 315)
• Australian Standard AS 1102
The designer will then use an interactive schematic capture toolto mix and match device components and place them on the schematic sheet. Then wire or connect the various component pins together to form a circuit schematic. This schematic will then be used as a template for later steps in the design process.
Building Component Libraries
Now that a circuit schematic has been completed, the designer must provide the design tool with additional information about the characteristics of each component to be used in the board layout. This will include the package size, pin layout, pin function, lead spacing, lead size of each component and housing. The electrical parameters for each pin are inputted, such as the capacitance and the impedance of each as well as their overall tolerances. If additional resistors or capacitors are to be used, the values and tolerance ranges of each discrete devise are added. All of this information is entered into a set of libraries one component at a time to be used later during circuit simulations.
Based on the detail component libraries built earlier, the designer will can now use a circuit analyzer to evaluate how well each circuit will perform over a range of operating conditions. In order to perform the simulation, SPICE (Simulation Program with Integrated Circuit Emphasis) models will have to be added to each of the component. Also, the software has to be capable of doing such simulation. The designer varies a number of electrical parameters over the expected tolerance ranges to determine how the circuit performs under worst-case conditions. These simulations ensure that each circuit will theoretically perform its intended function over the entire operating window and meet the design objectives called for. The simulator has built-in checker rules inputted previously that alert the designer to any violations or defects so that he can take corrective action to fix a problem once it arises.
Placing Components on PCBs
Once the circuit simulations have been completed, the actual layout of the design can begin. The designer will have to synchronize the circuitry from the schematic into the PCB. This is known as Forward annotation or ECO (Engineering Change Order) to PCB. The designer will be able to see how the physical components will look like when they are placed on the board.The designer puts components on the PCB using graphical tools such as PCB CAD software. Components are placed on the board by first grouping logical functions together. Within each functional grouping, components are then sited so that functions that communicate immediately are adjacent, keeping in mind that components that generate a greater degree of heat than others must be cooled properly. Furthermore, devices that must communicate externally are sited close to direct connectors. Ultimately, the primary goal is to make the most efficient usage of the board area while ensuring the circuit will function properly.
Sequencing Nets to High-Speed Rules
Today, most device components have sufficiently fast rise and fall times such that it's necessary to treat connection points as a transmission line. The high propagation speeds can result in transient effects that can compromise the signal integrity and degrade circuit performance to the point where the circuit will eventually fail. To avoid this undesired consequence, the node connections between the loads, terminations and drivers must be physically arranged to minimize signal interference. Such a predetermined arrangement of nodes is called sequencing or scheduling, and determines how best to connect the global nets to form proper transmission lines and ensure that improper stubs are not created. More importantly, this approach guarantees that termination occurs at the end of the each net.
Second Simulation: Timing and Transmission Lines
After the net sequencing is completed, the approximate special relationships between node points will need to be established. Since the physical X-Y location and connection sequences are known, this information can then be used to model the high-frequency switching characteristics of each net. These simulations evaluate deleterious signal distortion effects such as ringing, coupling, reflections and over and undershoot that can degrade circuit performance and even result in circuit failures. The simulations also calculate round-trip propagation delays between nodes to ensure that all of the timing parameters are within acceptable limits , which is often referred to as time-domain reflectometer (TDR). By running these simulations, the designer can address design issues and problems prior to routing and building the actual PCB prototype.
Sequencing and Placement Alterations
If the circuit simulators flag timing or signal propagation issues, the design placement will need to be adjusted to resolve the problem. This may involve rearranging the relationship between functions or adding additional termination points between components to reduce noise or signal issues. In some cases, it may involve rethinking the overall layout of the package. In the worst-case scenario, an additional layer of interconnects may be required that will drive up of the cost of assembly. In many cases, this sequence of function placement and circuit simulation will be repeated several times over until the circuit design meets all of its stated design objectives.
Testing the Routing and Placement
After all of of the circuit simulations have been completed, the physical layout of the board can begin. PCB designers can now begin to route wiring to connect all of the component devices together. For multilayer PCBs, the wiring complexity can be daunting. To assist them, designers often use CAD tools called rats-nest analyzers to determine if all of the signals can be fitted into the allotted PCB area. If an acceptable wiring solution cannot be obtained, the CAD tool can be used to adjust or change the routing to arrive at an acceptable routing diagram. Once the wire routing has been adjusted, the timing and transmission line simulations must be repeated. Similar to other steps in the design flow, this sequence may be repeated several times before arriving at a solution.
Routing the Printed Circuit Board
After a routing solution has been resolved, all of the interconnection points can be wired with copper traces to connect the nets in the different signal layers. For each design, this layout must adhere to strict wiring routing rules that define the proper line widths, line-to-line spacing and overlap rules that must be used to connect vias. During this process, some of the wiring can be done by the auto router, although usually the designer will lay out critical wiring by hand. Some auto routers can also check for ground rule violations after the wiring has been completed.
Double Checking Routing Results
Now that all of the wiring channels have been routed, the exact width and length of each connection is known. Additionally, the physical proximity of each wire to its neighbors in all of the different layers is now also known. This physical data is then reentered into the circuit analysis tool and the transient analysis is run again to check for timing and propagation delays, as well as noise or reflections that might impact signal integrity. If violations are detected, the designer will manually reroute the wiring to remove the problem. After correcting any violations, the designer will rerun the ground rule checker to verify that the wiring modifications do not introduce additional errors. Once the design is complete, it's checked against the net list to make sure that the circuit has been wired as intended. If the net list is acceptable, then a final check is performed on the Gerber data to make sure that none of the line-width and spacing ground rules have been violated.